From 1bce4bd7bcb11b8d8a6d322847f9cc602073975a Mon Sep 17 00:00:00 2001 From: tegwick Date: Tue, 26 May 2026 03:01:29 +0200 Subject: [PATCH] chore(workplan): activate CYA-WP-0002 (status: active) and seed ralph-workplan loop (HEUREKA, 20 iters); modernize instructions for task status canon (progress/wait); log activation to State Hub --- .gitignore | 1 + .../CYA-WP-0002-memory-integration-roadmap.md | 16 ++++++++++++---- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/.gitignore b/.gitignore index 36b13f1..a46e813 100644 --- a/.gitignore +++ b/.gitignore @@ -174,3 +174,4 @@ cython_debug/ # PyPI configuration file .pypirc +.claude/ralph-loop.local.md diff --git a/workplans/CYA-WP-0002-memory-integration-roadmap.md b/workplans/CYA-WP-0002-memory-integration-roadmap.md index 791b610..ecd7232 100644 --- a/workplans/CYA-WP-0002-memory-integration-roadmap.md +++ b/workplans/CYA-WP-0002-memory-integration-roadmap.md @@ -4,12 +4,12 @@ type: workplan title: "Memory Integration Roadmap: From Thin Ports to Profile-Driven phase-memory Backing" domain: capabilities repo: can-you-assist -status: proposed +status: active owner: grok topic_slug: foerster-capabilities created: "2026-05-26" updated: "2026-05-26" -state_hub_workstream_id: null +state_hub_workstream_id: "ef676f87-97f4-4635-a80d-4065730df87f" --- # CYA-WP-0002: Memory Integration Roadmap — From Thin Ports to Real phase-memory Backing @@ -46,6 +46,7 @@ This workplan directly addresses the largest gap identified in the Intent-vs-Sco id: CYA-WP-0002-T01 status: todo priority: high +state_hub_task_id: "d79840e3-2b24-48be-aac6-a8ed505153d4" ``` - Deep review of current phase-memory implementation, ports, profiles, phases, and activation/lifecycle planners (as of late May 2026). @@ -63,6 +64,7 @@ priority: high id: CYA-WP-0002-T02 status: todo priority: high +state_hub_task_id: "8bb93e26-0b2c-4ea7-8af0-6e70ca969b52" ``` - Replace or extend the T05 no-op ports with real calls into phase-memory (via its runtime or adapters). @@ -80,6 +82,7 @@ priority: high id: CYA-WP-0002-T03 status: todo priority: high +state_hub_task_id: "76c091c3-4978-48f1-996e-62a5fdbb6f12" ``` - Update `orchestrator.py` to consult memory ports when building `AssistanceRequest`. @@ -96,6 +99,7 @@ priority: high id: CYA-WP-0002-T04 status: todo priority: medium +state_hub_task_id: "bc77e793-b453-46b4-9442-4461af1ef43d" ``` - Extend the rule-based risk classifier (or add a memory-aware layer) to consider signals coming from memory (e.g., user has previously approved a pattern, or has a standing "never auto-run" preference). @@ -111,6 +115,7 @@ priority: medium id: CYA-WP-0002-T05 status: todo priority: high +state_hub_task_id: "d30f159c-3459-4c7b-ba31-990a73deaffb" ``` - Expand the test suite (building on T07) with memory-specific tests (in-memory fake phase-memory adapter, profile scenarios, error cases). @@ -127,6 +132,7 @@ priority: high id: CYA-WP-0002-T06 status: todo priority: medium +state_hub_task_id: "90e31eff-6ef7-4638-83d1-26bb64249862" ``` - Heavily update README and add Memory section with real before/after examples. @@ -144,9 +150,11 @@ priority: medium - **markitect-tool**: Likely needed for profile contracts if we want to go beyond hard-coded behavior. - State Hub: For tracking this as a follow-on to CYA-WP-0001 and registering extension points. -## Proposed Status & Activation +## Activation & Ralph Execution -This workplan is created in `proposed` status. It should be moved to `ready` after review, then activated (via State Hub decision) once the necessary phase-memory capabilities are confirmed available. +**Status: active** — ralph-workplan loop initialized (HEUREKA promise, max 20 iterations) to drive all 6 tasks to completion. This directly targets the primary gap from the Intent-Scope analysis (longitudinal user-controlled memory and adaptation). + +**Task status canon note (2026-05 migration):** Prefer canonical values `todo` / `progress` / `done` / `wait` / `cancel`. Legacy aliases accepted during window; AGENTS.md and workplans will be modernized in T06. ## References