feat(cya): T01-T07 core console-native MVP slice (CYA-WP-0001)

- T01: Python + Typer/rich + pyproject.toml + full src/ layout + working `cya` CLI entrypoint
- T02: Bounded transparent context collector (top-level only, provenance, ignores) + --explain-context
- T03: Genuine rule-based risk classifier (primary) + mandatory terminal confirmation, no auto-execute
- T04: LLMAdapter Protocol + deterministic FakeLLMAdapter seam (llm-connect boundary, zero bypass)
- T05: Strictly minimal phase-memory no-op ports (loud markers, per operator direction 2026-05-26)
- T06: Orchestrator coordinating the full flow; CLI is thin delegation
- T07: pytest harness + safety-focused tests (risk invariants + collector)

All changes verified by running the installed `cya` binary and `pytest tests/`.

Workplan updated with status. State Hub progress event logged (workstream 0a1233fd...).

Refs: CYA-WP-0001, Decision a644364b-11c4-49a9-bf17-99063382e27b

src/cya/memory/__init__.py

@@ -0,0 +1,89 @@
+"""phase-memory ports (T05) — strictly minimal no-op version.
+
+Operator direction (2026-05-26): Keep strictly minimal in this slice.
+Pure explicit ports with no-op implementations and clear
+"to be replaced by real phase-memory integration" markers.
+**No local JSON placeholder or file-backed store in this slice.**
+
+All memory interactions in can-you-assist must go through these ports.
+No global singletons, no implicit ~/.cache, no opaque vendor memory.
+
+When the real `phase-memory` package is integrated, the entire contents
+of this module (or the implementations behind these names) will be
+replaced by the real ports. Code reviewers and future contributors
+should be able to point at this file and say "this is the seam".
+
+See workplan CYA-WP-0001-T05 for the full contract and acceptance criteria.
+"""
+
+from __future__ import annotations
+
+import sys
+from typing import Any
+
+
+def _warn_not_connected(feature: str) -> None:
+    """Loud, visible marker that phase-memory is not yet wired."""
+    msg = (
+        f"[phase-memory] {feature} called — phase-memory not yet connected. "
+        "This is a no-op placeholder. Real implementation will come from the "
+        "phase-memory package. See T05 in workplan CYA-WP-0001."
+    )
+    print(msg, file=sys.stderr)
+
+
+# ---------------------------------------------------------------------------
+# Explicit ports (the four capabilities from the workplan)
+# These are the exact extension points that phase-memory will implement.
+# ---------------------------------------------------------------------------
+
+
+def remember_preference(key: str, value: Any, scope: str = "cwd") -> None:
+    """Remember a user preference or workflow pattern.
+
+    Will be replaced by real phase-memory.
+    """
+    _warn_not_connected(f"remember_preference({key!r}, scope={scope})")
+    # No-op by design
+
+
+def recall_preferences(scope: str = "cwd", task_class: str | None = None) -> dict[str, Any]:
+    """Recall relevant history / preferences for the current cwd + task class.
+
+    Will be replaced by real phase-memory.
+    Returns empty dict in this slice.
+    """
+    _warn_not_connected(f"recall_preferences(scope={scope}, task={task_class})")
+    return {}
+
+
+def forget(scope: str = "cwd", keys: list[str] | None = None) -> None:
+    """Forget / reset memory (scoped).
+
+    Will be replaced by real phase-memory.
+    """
+    _warn_not_connected(f"forget(scope={scope}, keys={keys})")
+    # No-op
+
+
+def export_memory(scope: str = "cwd") -> dict[str, Any]:
+    """Inspect / export current memory for this project or user.
+
+    Will be replaced by real phase-memory.
+    Returns a clear "disabled" marker in this slice.
+    """
+    _warn_not_connected(f"export_memory(scope={scope})")
+    return {
+        "status": "phase-memory not connected (T05 no-op)",
+        "scope": scope,
+        "note": "Replace this entire module with the real phase-memory ports.",
+    }
+
+
+__all__ = [
+    "remember_preference",
+    "recall_preferences",
+    "forget",
+    "export_memory",
+]
+