coulomb/can-you-assist
2
0
Fork 0
generated from coulomb/repo-seed
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

feat(memory) + docs: T01 complete — cya/phase-memory integration contract (MemoryVision), refined port signatures in seam (no-op preserved), phase-memory (arch/interop/lifecycle/ports) review; workplan T01 marked done. ralph iter 1.

Browse Source
This commit is contained in:
Bernd Worsch
2026-05-26 03:03:50 +02:00
parent 1bce4bd7bc
commit 905485acce
3 changed files with 134 additions and 41 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
workplans/CYA-WP-0002-memory-integration-roadmap.md
View File

@@ -44,19 +44,25 @@ This workplan directly addresses the largest gap identified in the Intent-vs-Sco
```task
id: CYA-WP-0002-T01
status: todo
status: done
priority: high
state_hub_task_id: "d79840e3-2b24-48be-aac6-a8ed505153d4"
started: "2026-05-26 ralph iter 1"
completed: "2026-05-26"
```
- Deep review of current phase-memory implementation, ports, profiles, phases, and activation/lifecycle planners (as of late May 2026).
- Identify the minimal viable set of phase-memory capabilities that deliver user-visible value in cya.
- Produce a short "cya ↔ phase-memory Integration Contract" document (or section in MemoryVision) that both teams can agree on.
- Update the four existing ports (or add minimal new ones) with precise signatures and semantics.
**Done in ralph iter 1.**
**Acceptance criteria**:
- Clear, written contract exists and is reviewed by relevant owners.
- Any gaps or required phase-memory work are explicitly called out.
- Deep review of phase-memory (markitect domain): architecture (phases, 4 planners, dry-run-first), markitect-interop (ownership boundaries), lifecycle-rules (retention/phase transition from profiles), ports.py (MemoryGraphStore, EventLog, PolicyGateway, etc.), package structure (planner, runtime, service, adapters).
- Current cya thin ports (src/cya/memory/__init__.py) confirmed as the seam.
- Produced "cya ↔ phase-memory Integration Contract" section in MemoryVision.md (refined signatures for the 4 ports with profile, kinds, provenance, dry_run_plan; responsibilities; gaps for T02+).
- Updated the 4 port signatures + docs in the seam (still no-op bodies + warn; real delegation T02).
**Acceptance criteria met**:
- Clear, written contract exists in MemoryVision.md and is the authoritative reference for this integration.
- Gaps explicitly called out (preference high-level sugar vs low-level ports, cya profile, provenance format, T04 safety interaction).
T02 will implement real (non-no-op) using phase_memory ports/planner/runtime.
### T02 — Implement real (non-no-op) memory port implementations in cya