4 Commits

Author	SHA1	Message	Date
tegwick	e8f7320bb4	feat(memory): T03 complete — memory wired into orchestrator (consult + --explain-context surface + context to LLM + render); T01-T03 now done in workplan (ralph iters 1-3)	2026-05-26 03:13:06 +02:00
tegwick	905485acce	feat(memory) + docs: T01 complete — cya/phase-memory integration contract (MemoryVision), refined port signatures in seam (no-op preserved), phase-memory (arch/interop/lifecycle/ports) review; workplan T01 marked done. ralph iter 1.	2026-05-26 03:03:50 +02:00
tegwick	1bce4bd7bc	chore(workplan): activate CYA-WP-0002 (status: active) and seed ralph-workplan loop (HEUREKA, 20 iters); modernize instructions for task status canon (progress/wait); log activation to State Hub	2026-05-26 03:01:29 +02:00
tegwick	aea790622a	feat(workplan): create CYA-WP-0002 focused on MemoryVision realization ... New workplan: Memory Integration Roadmap — moving from the thin T05 no-op ports toward real, profile-driven phase-memory integration. Directly addresses the primary gap identified in the recent Intent-vs-Scope analysis and the new MemoryVision.md. Refs: MemoryVision.md, CYA-WP-0001, history/2026-05-26 gap analysis	2026-05-26 02:43:22 +02:00