tegwick 19e80cc9bc CYA-WP-0005 T02 done (ralph iter 2): Formalize Profile 0 baseline everywhere ...

- MemoryVision.md: Large new 'Profile 0 Baseline (Post-0003 / Current Shipped)' section with exact ports, activation logic, retrospection, safety invariants, usage sites, and relationship to 1–3 (plus the prior research section from T01).
- src/cya/memory/__init__.py: Updated module docstring to declare Profile 0 reality + references to MemoryVision + CYA-WP-0005.
- src/cya/orchestrator.py: Updated docstring with Profile 0 memory wiring note.
- SCOPE.md: Named Profile 0 explicitly in delivered slices and core capabilities.
- tests/test_memory.py: Added two new explicit 'Profile 0' tests + comments asserting provenance markers, kinds, activation_context support (T02 acceptance).
- README.md + AGENTS.md: Added Profile 0 mentions + links to the workplan.

All T02 acceptance criteria met. Ralph loop active. Next: T03 (full Profiles 1–3 definitions + matrix).

2026-05-27 20:01:51 +02:00

..

conftest.py

feat(cya): T01-T07 core console-native MVP slice (CYA-WP-0001)

2026-05-26 02:19:13 +02:00

test_collector.py

feat(cya): T01-T07 core console-native MVP slice (CYA-WP-0001)

2026-05-26 02:19:13 +02:00

test_memory.py

CYA-WP-0005 T02 done (ralph iter 2): Formalize Profile 0 baseline everywhere

2026-05-27 20:01:51 +02:00

test_risk.py

feat(cya): T01-T07 core console-native MVP slice (CYA-WP-0001)

2026-05-26 02:19:13 +02:00