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6018e429307926c0ee9c15dc73473c60bbcc9e3a
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8 Commits

Author SHA1 Message Date
tegwick
a0f79af2ab Normalize agent instructions and workplan frontmatter (STATE-WP-0067) 
- Align agent files with on-disk workplan prefixes (infer from workplan ids)
- Set workplan domain to registered domain_slug; add topic_slug where applicable
- Repair frontmatter delimiter formatting; migrate legacy task status literals
- Regenerate AGENTS.md, CLAUDE.md, and .claude/rules from State Hub templates
 2026-06-22 23:16:24 +02:00
tegwick
f4e965cc04 Add Claude Code support, credential routing polish, and CYA-WP-0006 
Mirror sibling-repo Claude setup (CLAUDE.md + .claude/rules/*), align
AGENTS.md with fleet credential-routing template, and close housekeeping
gaps (WP-0002-T05 done, WP-0005 status note). Draft CYA-WP-0006 for
Profile 1 production hardening as the proposed next slice.
 2026-06-19 20:33:13 +02:00
tegwick
b7a2cc48ba chore(docs+tests): complete T05 + T06 for CYA-WP-0002. All 6 tasks done. README Memory section, AGENTS update, full test coverage for real memory + safety. Workplan retired. 2026-05-26 07:01:12 +02:00
tegwick
98a43f5671 feat(safety): T04 complete — memory signals integrated into rule-based risk classifier (conservative only; never bypasses confirmation). Verified live. T01-T04 now done. 2026-05-26 03:17:38 +02:00
tegwick
e8f7320bb4 feat(memory): T03 complete — memory wired into orchestrator (consult + --explain-context surface + context to LLM + render); T01-T03 now done in workplan (ralph iters 1-3) 2026-05-26 03:13:06 +02:00
tegwick
905485acce feat(memory) + docs: T01 complete — cya/phase-memory integration contract (MemoryVision), refined port signatures in seam (no-op preserved), phase-memory (arch/interop/lifecycle/ports) review; workplan T01 marked done. ralph iter 1. 2026-05-26 03:03:50 +02:00
tegwick
1bce4bd7bc chore(workplan): activate CYA-WP-0002 (status: active) and seed ralph-workplan loop (HEUREKA, 20 iters); modernize instructions for task status canon (progress/wait); log activation to State Hub 2026-05-26 03:01:29 +02:00
tegwick
aea790622a feat(workplan): create CYA-WP-0002 focused on MemoryVision realization 
New workplan: Memory Integration Roadmap — moving from the thin T05 no-op ports toward real, profile-driven phase-memory integration.

Directly addresses the primary gap identified in the recent Intent-vs-Scope analysis and the new MemoryVision.md.

Refs: MemoryVision.md, CYA-WP-0001, history/2026-05-26 gap analysis
 2026-05-26 02:43:22 +02:00