4 Commits

Author	SHA1	Message	Date
tegwick	98a43f5671	feat(safety): T04 complete — memory signals integrated into rule-based risk classifier (conservative only; never bypasses confirmation). Verified live. T01-T04 now done.	2026-05-26 03:17:38 +02:00
tegwick	e8f7320bb4	feat(memory): T03 complete — memory wired into orchestrator (consult + --explain-context surface + context to LLM + render); T01-T03 now done in workplan (ralph iters 1-3)	2026-05-26 03:13:06 +02:00
tegwick	905485acce	feat(memory) + docs: T01 complete — cya/phase-memory integration contract (MemoryVision), refined port signatures in seam (no-op preserved), phase-memory (arch/interop/lifecycle/ports) review; workplan T01 marked done. ralph iter 1.	2026-05-26 03:03:50 +02:00
tegwick	637919dd8c	feat(cya): T01-T07 core console-native MVP slice (CYA-WP-0001) ... - T01: Python + Typer/rich + pyproject.toml + full src/ layout + working `cya` CLI entrypoint - T02: Bounded transparent context collector (top-level only, provenance, ignores) + --explain-context - T03: Genuine rule-based risk classifier (primary) + mandatory terminal confirmation, no auto-execute - T04: LLMAdapter Protocol + deterministic FakeLLMAdapter seam (llm-connect boundary, zero bypass) - T05: Strictly minimal phase-memory no-op ports (loud markers, per operator direction 2026-05-26) - T06: Orchestrator coordinating the full flow; CLI is thin delegation - T07: pytest harness + safety-focused tests (risk invariants + collector) All changes verified by running the installed `cya` binary and `pytest tests/`. Workplan updated with status. State Hub progress event logged (workstream 0a1233fd...). Refs: CYA-WP-0001, Decision a644364b-11c4-49a9-bf17-99063382e27b	2026-05-26 02:19:13 +02:00