tegwick 98a43f5671 feat(safety): T04 complete — memory signals integrated into rule-based risk classifier (conservative only; never bypasses confirmation). Verified live. T01-T04 now done.

2026-05-26 03:17:38 +02:00

..

cli

feat(cya): T01-T07 core console-native MVP slice (CYA-WP-0001)

2026-05-26 02:19:13 +02:00

context

feat(cya): T01-T07 core console-native MVP slice (CYA-WP-0001)

2026-05-26 02:19:13 +02:00

llm

feat(cya): T01-T07 core console-native MVP slice (CYA-WP-0001)

2026-05-26 02:19:13 +02:00

memory

feat(memory) + docs: T01 complete — cya/phase-memory integration contract (MemoryVision), refined port signatures in seam (no-op preserved), phase-memory (arch/interop/lifecycle/ports) review; workplan T01 marked done. ralph iter 1.

2026-05-26 03:03:50 +02:00

safety

feat(safety): T04 complete — memory signals integrated into rule-based risk classifier (conservative only; never bypasses confirmation). Verified live. T01-T04 now done.

2026-05-26 03:17:38 +02:00

__init__.py

feat(cya): T01-T07 core console-native MVP slice (CYA-WP-0001)

2026-05-26 02:19:13 +02:00

orchestrator.py

feat(safety): T04 complete — memory signals integrated into rule-based risk classifier (conservative only; never bypasses confirmation). Verified live. T01-T04 now done.

2026-05-26 03:17:38 +02:00