New workplan: Memory Integration Roadmap — moving from the thin T05 no-op ports toward real, profile-driven phase-memory integration.
Directly addresses the primary gap identified in the recent Intent-vs-Scope analysis and the new MemoryVision.md.
Refs: MemoryVision.md, CYA-WP-0001, history/2026-05-26 gap analysis
- New MemoryVision.md outlining long-term vision for phase-memory integration in cya (profiles, phases, lifecycle, ports)
- Persisted full Intent-vs-Scope gap analysis in history/
- Updated SCOPE.md to reflect post-MVP reality and MemoryVision direction
- Minor cross-references in AGENTS.md and the CYA-WP-0001 workplan
This lays the foundation for the next workplan (CYA-WP-0002) focused on realizing the MemoryVision.
Refs: MemoryVision.md, history/2026-05-26-CYA-Intent-Scope-Gap-Analysis.md, CYA-WP-0001 T05/T08
- Frontmatter: status `ready` → `active`
- Added "Status Update — 2026-05-26 (Activated)" section documenting
the resolved stack choices and the specific direction on T03 (safety)
and T05 (phase-memory).
- Annotated the T03 and T05 task descriptions with the operator's
explicit guidance (rule-based risk assessment first + ADR requirement;
strictly minimal no-op ports for memory).
- Linked the resolved State Hub Decision `a644364b-11c4-49a9-bf17-99063382e27b`.
- Updated Current Evidence to reflect bootstrap completion and activation.
This authorizes implementation of the narrow console-native MVP slice
to begin (starting with T01).
Resolves: State Hub Decision D1 (now `resolved`)
